The application relates to an active plate including a storage capacitor and to a method of making the active plate, and in particular to a storage capacitor, pixel structure and method for making an active plate as used for example in an active matrix liquid crystal display.
Active matrix liquid crystal displays (AMLCDs) are widely used for providing high quality displays in a number of applications, for example laptop personal computers. In such active matrix liquid crystal displays, transistors corresponding to individual pixel electrodes are used to drive the liquid crystal display. The transistors are generally thin film transistors (TFTs).
Conventionally, active matrix liquid crystal displays include an active plate carrying the active pixel electrodes and corresponding TFT drive transistors and an opposed passive plate supporting a counter electrode, with liquid crystal sandwiched between the active and passive plates.
A conventional active plate of an AMLCD is illustrated in top view in FIG. 1 and in section along Axe2x80x94A in FIG. 2. The active plate is formed on a substantially flat substrate 1. Row electrodes 2 and column electrodes 4 extend across the active plate in substantially perpendicular directions. Gate electrodes 6 extend off the row electrodes 2 to form the bottom gate of each pixel element. Insulating regions 8 separate the row and column electrodes. Capacitor electrodes 10 likewise extend across the active matrix, parallel to the row electrodes.
An insulating layer 16 is formed over the gate electrode to form the gate insulating layer and over the capacitor electrode to form the capacitor dielectric. A semiconductor region 12 is formed over the insulating layer 16. The semiconductor region includes a lower undoped amorphous silicon layer 14 extending from a source region 34 to a drain region 36 over the gate insulating layer 16 and highly doped contact regions 18 at the source and drain regions 34,36. A source contact 32 connects to the source region 34 and a drain contact 30 connects to the drain region 36. A spur 24 extends from the column electrode 4 to connect to the source contact 32.
The semiconductor region 12, gate electrode 6, insulating layer 16 and source and drain contacts 18 form a thin film transistor (TFT) structure.
The TFT structure is covered by an insulating layer 20. A via hole 22 connects through this insulating layer to the drain contact 30. A transparent pixel electrode 26, generally formed of indium tin oxide, connects to the drain contact 30 through the via hole 22.
A storage capacitor is formed between the pixel electrode 26 and the capacitance line 10. To this end, a top capacitor electrode 28 is formed in each pixel above the insulating layer 16 over the storage capacitor electrode 10. The pixel electrode 26 connects to the top capacitor electrode 28 through a via hole 22.
The single pixel electrode and TFT structure described above is repeated across the substrate 1 to define a matrix of pixels.
Typical processes for making arrays of pixel electrodes to form active plates use photolithography and etching to pattern the various layers used to make up the structure. Many processes employ five mask layers, although some processes have been proposed using only four mask layers. The need to deposit material layers, define photoresist on each layer and then etch or develop away as much as 95% of each material layer limits possible cost savings. Moreover, photolithography is a high cost process which uses tools with a high capital cost, limited throughput and which consumes large quantities of costly photoresist and developer.
Accordingly, there have been proposals to use lower cost lower resolution patterning processes to fabricate active matrix plates. For example, printing processes have been proposed. Unfortunately, printing processes have poor resolution and alignment accuracy compared with conventional photolithography. Moreover, printing processes such as gravure offset tend to leave hairs or tails on materials extending out from the trailing edges of features. These hairs or tails can cause short circuits. Accordingly, it is very difficult to manufacture active plates using printing technologies.
There is thus a need for a method of manufacturing active plates using lower resolution processes, and for a corresponding design of active plates.
According to the invention there is provided an active plate comprising a substrate; a first metallisation layer defining gate electrodes and first storage capacitor electrodes extending longitudinally across the substrate; a second metallisation layer defining source and drain electrodes and second storage capacitor electrodes; a semiconductor body layer forming thin film transistor bodies between the source and drain electrodes; and an insulation layer between first and second storage capacitor electrodes; wherein the second electrode is formed from a plurality of fingers extending across the first electrode.
An important factor in active matrix liquid crystal display performance is the kick back voltage. This is proportional to the parasitic gate pixel capacitance in the switching TFT divided by the total pixel capacitance. Some process variations can cause the TFT parasitic capacitance to vary, and hence the kickback voltage to vary also. This is a particular problem with arrangements which use lower definition patterning processes such as printing, although the problem applies to some extent in all active matrix liquid crystal displays.
This variation in voltage does not just occur in AMLCDs, but also in other structures that use an active plate with TFTs and storage capacitors. One example of such a structure is an X-ray detector of the type having an array of addressed elements and storage capacitors.
In the active plate according to the invention, an increase in width of the drain electrode will tend to be matched by an increase in width of the fingers, since both are formed in the second metallisation layer and patterned using the same process. When used in an active matrix structure the kick back voltage, which is dependent on the ratio of these two quantities, will accordingly be much less dependent on variability in the patterning process used to define the drain electrode and the fingers capacitor electrode.
The plurality of fingers may be electrically connected together by at least one longitudinal element formed in the second metallisation layer, by separately connecting each finger to the pixel electrode through respective vias, or otherwise.
The width of the fingers may be from half to double the width of the drain electrode, for effective cancellation, preferably from 0.8 times to 1.2 times.
The active plate may incorporate features to permit one or more layers to be formed from a lower definition patterning process. For example, the semiconductor body may extend longitudinally over the gate electrode, so that any hairs or tails extending from the semiconductor body will remain over the gate electrode without significantly affecting the structure.
The drain electrode may extend across the full width of the semiconductor body and the gate electrode. This simple arrangement makes it easier for the semiconductor body and gate electrode to be formed in a lower resolution process. Moreover, when combined with a second electrode overlapping the edges of the first electrode, the kick back voltage may be less sensitive to variation in the width of a metallisation layer forming the first storage capacitor electrode and the gate electrode of a TFT.
In order to combine the plurality of fingers and the overlapping electrodes, embodiments of the invention form the second electrode from a plurality of fingers extending laterally across the full width of the first electrode.
The gate electrodes may extend longitudinally across the substrate with substantially constant width.
The active plate may be incorporated in a liquid crystal display having liquid crystal between active and passive plates.
The invention also relates to a method of manufacture of an active plate, comprising the steps of: depositing and patterning using a lower definition patterning process a first metallisation layer on a substrate, the first metallisation layer defining gate electrodes and first storage capacitor electrodes extending longitudinally across the substrate; depositing an insulation layer; depositing and patterning using a lower definition patterning process a semiconductor body layer forming thin film transistor bodies; and depositing and patterning using a higher definition process a second metallisation layer defining source and drain electrodes and second storage capacitor electrodes, wherein the second storage capacitor electrode is patterned to have a plurality of separate fingers extending across the substrate.
The overlapping second storage capacitor electrode reduces adverse effects from the use of lower definition processes used to pattern some of the layers, especially the first metallisation layer. In particular, the device thus manufactured may exhibit a lower variation in kick back voltage than would otherwise be the case.
In embodiments, the higher definition process may be photolithography and the lower definition process may be printing.
The drain electrode may extend across the width of the gate electrode.